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--- en:multiasm:papc:chapter_6_3 [2025/12/22 11:34] – [x86 registers] ktokarz
+++ en:multiasm:papc:chapter_6_3 [2026/04/01 14:03] (current) – [ZMM registers] ktokarz
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+====== Register Set ======
+As x86 processors evolved, the set of available registers and their size expanded. Newer processors added more general-purpose registers, and new registers related to the FPU and vector extensions were added. In this chapter, we discuss the registers available to the programmer, from the 8086 up to modern 64-bit processors.
+===== x86 registers =====
+The 8086 processor has seven general-purpose registers for data storage, data manipulation and indirect addressing. Four registers: AX, BX, CX and DX can be accessed in two 8-bit halves. The lower half has the "L" letter, and the upper half has the "H" letter in the register name instead of "X". General-purpose registers are presented in Fig {{ref>gpregistresx86}}.
+<figure gpregistresx86>
+{{ :en:multiasm:cs:GP_registers_x86.png?600 |Illustration of general purpose registers in x86 16-bit processor}}
+<caption> General-purpose registers in 16-bit 8086 processor</caption>
+</figure>
+They have some special functions, as listed below.
+  * AX - Accumulator, used for general data manipulation; some instructions work only with the accumulator.
+  * BX - Base register, used for indirect addressing in base addressing mode.
+  * CX - Counter register, used for iteration counting for loops and repeated instructions.
+  * DX - Data register, used as an extension of the accumulator, and for I/O address space addressing.
+  * SI - Source index, used for indirect index addressing of source data tables or strings.
+  * DI - Destination index, used for indirect index addressing of destination data tables or strings.
+  * BP - Base pointer, often used for accessing data on the stack without the need for the stack pointer modification.
+Some registers have special purposes.
+  * SP - Stack pointer, used for stack manipulation, automatically handles storing and retrieving the return address of procedures while calling and returning.
+  * IP - Instruction pointer, points to the next instruction to be executed; sometimes called program counter.
+These registers are presented in Fig {{ref>spregistresx86}}.
+<figure spregistresx86>
+{{ :en:multiasm:cs:special_registers_x86.png?600 |Illustration of stack pointer and instruction pointer registers in an x86 16-bit processor}}
+<caption>Stack pointer and instruction pointer in 16-bit 8086 processor</caption>
+</figure>
+Every processor has a register containing bits used to inform the software about the state of the ALU, about the result of the last arithmetic or logic operation, and used to control the behaviour of the CPU. In x86, it is called the Flags register, and is shown in fig {{ref>flagsx86}}.
+<figure flagsx86>
+{{ :en:multiasm:cs:flags_register_x86.png?500 |Illustration of the flags register in x86 16-bit processor}}
+<caption>Flags register in 16-bit 8086 processor</caption>
+</figure>
+The meaning of informational flags is as follows:
+  * CF - Carry flag, set if an operation generates a carry or borrow; for example, if the result of an addition is larger than 16 bits. Used for unsigned arguments.
+  * PF - Parity flag, set if the result of an operation contains an even number of bits equal to "1".
+  * AF - Auxiliary Carry flag, similar to CF but informs about the carry or borrow from the 3rd to the 4th bit. It is used for BCD calculations.
+  * ZF - Zero flag, set if the result of an operation is zero.
+  * SF - Sign flag, it is a copy of the most significant bit of the result.
+  * OF - Overflow flag, set if the result of an operation is too large or small to fit in the destination operand. Used for signed arguments.
+Control flags allow modification of the processor's behaviour:
+  * TF - Trap flag, used for debugging to execute a program one instruction at a time.
+  * IF - Interrupt flag, if set, interrupts are enabled.
+  * DF - Direction flag, determines the direction of string operations. If cleared, string operations work from lower to higher addresses; if set, they operate in the opposite direction.
+The 8086, being a 16-bit processor, can address memory in real mode only (please refer to section "Segmented addressing in real mode"). It has four segment registers:
+  * CS - Code segment register, used together with IP to access the instruction in the code segment.
+  * DS - Data segment register, used to access the default data segment.
+  * ES - Extra segment register, used to access an additional data segment.
+  * SS - Stack segment register, used together with SP or BP to access elements on the stack.
+Segment registers are shown in Fig {{ref>segmentregsx86}}.
+<figure segmentregsx86>
+{{ :en:multiasm:cs:segment_registers_x86.png?200 |Illustration of the segment registers in x86 16-bit processor}}
+<caption>Segment registers in 16-bit 8086 processor</caption>
+</figure>
+===== IA-32 registers =====
+Starting from the 80386 processor general-purpose registers, stack pointer, instruction pointer, and flags register were extended to 32 bits. Inter added an extra 16 bits to each of them, leaving the possibility to access the lower half as in previous models. For example, an accumulator can be accessed as 32-bit EAX, 16-bit AX, and 8-bit AH and AL. The resulting register set is shown in Fig {{ref>GPregsIA32}}.
+<figure GPregsIA32>
+{{ :en:multiasm:cs:GP_registers_IA32.png?600 |Illustration of the register set in IA-32 32-bit processor}}
+<caption>Register set in 32-bit IA-32 processors</caption>
+</figure>
+Similarly, the IP and flags registers were extended to 32-bit size (fig.{{ref>eflagsIA32}}). Additional bits in the Eflags register are mainly used for handling the virtual memory mechanism and memory protection. They are used mainly by the operating system software, so we will not focus on details here.
+<figure eflagsIA32>
+{{ :en:multiasm:cs:eflags_register_IA32.png?600 |Illustration of the Eflags register in IA-32 32-bit processor}}
+<caption>Eflags register in 32-bit IA-32 processors</caption>
+</figure>
+In 32-bit machines, two additional segment registers were added: FS and GS (fig.{{ref>segregsIA32}}). It is worth noticing that all segment registers are still 16 bits long, but there are hidden parts, not available directly to the programmer, used for storage of descriptors (refer to the section "Segmented addressing in protected mode").
+<figure segregsIA32>
+{{ :en:multiasm:cs:segment_registers_IA32.png?200 |Illustration of segment registers in IA-32 32-bit processor}}
+<caption>Segment registers in 32-bit IA-32 processors</caption>
+</figure>
+===== x64 registers =====
+The 64-bit extension to the IA-32 architecture was proposed by AMD. Registers were extended to 64 bits, and additionally, eight new general-purpose registers were added. They obtained the names R8 - R15. All registers (including already known registers) can be accessed as 64-bit, 32-bit lower-order half, 16-bit lower-order quarter (word) and 8-bit lower-order byte. Registers are presented in fig.{{ref>GPregsx64}} and in fig.{{ref>newregsx64}}. The Eflags register is extended to 64 bits and named Rflags. The upper 32 bits of the Rflags are reserved.
+<figure GPregsx64>
+{{ :en:multiasm:cs:GP_registers_x64.png?600 |Illustration of the register set in x64 64-bit processor}}
+<caption>Register set in 64-bit x64 processors</caption>
+</figure>
+<figure newregsx64>
+{{ :en:multiasm:cs:new_registers_x64.png?600 |Illustration of new registers in x64 64-bit processor}}
+<caption>New registers in 64-bit x64 processors</caption>
+</figure>
+===== FPU registers =====
+The floating point unit, sometimes referred to as x87, works using eight 80-bit data registers, as presented in figure {{ref>fpudataregs}}. They are organised as a stack, so data items are pushed into the top register. Calculations are done using the top of the stack and another register, usually the next one. Registers are named ST(0) to ST(7), where ST(0) is the top of the stack; register ST(7) is the bottom. The ST name is another way to refer to ST(0). The registers contain the sign bit, exponent part and significand part, encoded according to the IEEE754 standard. Please refer to the section about data encoding and to the section about the FPU description for details of floating-point instructions.
+<figure fpudataregs>
+{{ :en:multiasm:cs:fpu_data_registers.png?600 |Illustration of the register set in FPU coprocessor}}
+<caption>Register set in x87 Floating Point Unit coprocessor</caption>
+</figure>
+There are also control and status registers in the Floating Point Unit as presented in figure {{ref>fpucontrolregs}}.
+<figure fpucontrolregs>
+{{ :en:multiasm:cs:fpu_control_registers.png?600 |Illustration of the control registers FPU coprocessor}}
+<caption>Control registers in x87 Floating Point Unit coprocessor</caption>
+</figure>
+FPU instruction pointer, data pointer and last opcode registers are used for cooperation with the main processor. The Tag register (figure {{ref>fputagreg}}) holds the 2-bit information of the states of each data register. It helps to manage the stack organisation of the data registers.
+<figure fputagreg>
+{{ :en:multiasm:cs:fpu_tag_register.png?400 |Illustration of the TAG register in FPU coprocessor}}
+<caption>TAG register in x87 Floating Point Unit coprocessor</caption>
+</figure>
+The Status Word register contains information about the FPU's current state, including the top of the stack, exception flags, and condition codes (figure {{ref>fpustatereg}}). The latter ones inform about the result of the last operation, similarly to the flags in the RFlag register.
+<figure fpustatereg>
+{{ :en:multiasm:cs:fpu_sw_register.png?500 |Illustration of the Status Word register in FPU coprocessor}}
+<caption>Status Word register in x87 Floating Point Unit coprocessor</caption>
+</figure>
+The Control Word register (figure {{ref>fpucontrolreg}} makes it possible to enable or disable exceptions, control the precision of calculations and rounding of their results. The infinity bit is not meaningful in new processors.
+<figure fpucontrolreg>
+{{ :en:multiasm:cs:fpu_cw_register.png?500 |Illustration of the Control Word register in FPU coprocessor}}
+<caption>Control Word register in x87 Floating Point Unit coprocessor</caption>
+</figure>
+===== MMX registers =====
+MMX instructions are executed with the use of 64-bit packed data. Intel decided to map MMX registers onto the existing FPU registers. The MMX unit has 8 registers named MM0 - MM7, as presented in figure {{ref>mmxregs}}. Because they are physically the same as FPU registers, it is not possible to mix freely MMX and FPU instructions.
+<figure mmxregs>
+{{ :en:multiasm:cs:mmx_registers.png?600 |Illustration of the MMX registers}}
+<caption>MMX registers</caption>
+</figure>
+===== XMM registers =====
+SSE instructions are executed with the use of 128-bit packed data. To perform calculations, new 128-bit registers were introduced. The SSE unit has 8 registers named XMM0 - XMM7. Because these registers are separate from all previous ones, there are no conflicts between SSE and other instructions.
+To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.
+<figure mxcsrreg>
+{{ :en:multiasm:cs:mxcsr_register.png?500 |Illustration of the MXCSR SSE control register}}
+<caption>MXCSR control register for SSE unit</caption>
+</figure>
+===== YMM registers =====
+The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16.
+===== ZMM registers =====
+ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available.
+XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}}
+<figure xyzmmregs>
+{{ :en:multiasm:cs:xyzmm_register.png?600 |Illustration of the relation between XMM, YMM and ZMM registers}}
+<caption>The relation between XMM, YMM and ZMM registers</caption>
+</figure>
+Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors. They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions.
+===== Additional registers =====
+In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable.
+Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)).